1. Field of the Invention
The present invention relates generally to electrical circuits, and more particularly but not exclusively to power on reset circuits.
2. Description of the Background Art
A power on reset circuit generates a signal indicative of the status of a monitored power source provided to the circuit. For example, the power on reset circuit may generate a logical LOW signal when the monitored power source is below a trip point, and a logical HIGH signal when the monitored power source is above the trip point. The signal may be provided to another circuit that operates depending on the state of the signal. For example, the other circuit may be reset when the signal indicates that the monitored power source is below the trip point.
FIG. 1 shows a schematic diagram of an exemplary power on reset (“POR”) circuit 100. As shown in FIG. 1, POR circuit 100 comprises a main circuit 180 and a translation circuit 190. Main circuit 180 includes a resistor ladder comprising resistors R1, R2, R3, and R4. The voltage across R4, which is a scaled version of the monitored external voltage Vcch, is coupled to control the gate of transistor M1. When the voltage on the gate of transistor M1 is below its threshold voltage (the trip point in this example), transistor M1 is OFF, thereby providing Vcch on node 110 via resistors R6 and R5. When the voltage on the gate of transistor M1 is above the trip point, transistor M1 is ON, thereby pulling node 110 to ground. Capacitor C1 sets the pulse width and brownout sensitivity of POR circuit 100. Capacitor C2 prevents stray capacitance from causing the output of transitor M1 (i.e., node 110) to be OFF when resistor R6 is very weak. Transistor M2 provides some hysteresis by modifying the falling trip point of POR circuit 100. The effects of transistor M2 and capacitors C1 and C2 are not relevant to the present disclosure, and will not be taken into account in the following analysis in the interest of clarity.
In a typical application, the signal on node 110, which is indicative of the state of Vcch, may be directly provided to another circuit. However, in applications where there is voltage incompatibility between main circuit 180 and the other circuit, a translation circuit may be employed between the two circuits. In circuit 100, translation circuit 190 allows the signal on node 110 of main circuit 180 to be provided to a low voltage, single gate oxide (SGOX) transistor coupled to node 130.
One problem with circuit 100 is that it has a tendency to not provide a correct output signal on node 130 during brownouts. For example, the POR output signal on node 130 may not indicate the correct state of Vcch when Vcch dips below the trip point. FIG. 2 shows waveforms illustrating improper operation of a power on reset circuit. In the examples of FIG. 2 and subsequently described FIG. 3, a logical HIGH POR output indicates a proper external voltage Vcch, while a logical LOW POR output indicates a brownout. In the example of FIG. 2, the POR output does not pull down to ground (i.e., logical LOW) even when Vcch goes below the trip point during a brownout (see arrows 212 and 213). FIG. 3 shows waveforms illustrating proper operation of a power on reset circuit. As shown in FIG. 3, the POR output should pull to ground (see arrows 312 and 313) when Vcch dips below the trip point, indicating to other circuits that a brownout has occurred.